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| 1 for more information www.linear.com/LTC4020 v in (v) 5 efficiency (%) power (w) 100 100 90 80 70 60 50 40 30 20 10 0 95 90 85 80 75 10 15 4020 ta01b 20 3025 v out = 14v efficiency input power p(loss) typical a pplica t ion fea t ures descrip t ion 55v buck-boost multi-chemistry battery charger the lt c ? 4020 is a high voltage power manager provid - ing powerpath? instant-on operation and high efficiency batter y charging over a wide voltage range . an onboard buck-boost dc/ dc controller operates with battery and/or system voltages above, below, or equal to the input voltage. the LTC4020 seamlessly manages power distribution between battery and converter outputs in response to load variations, battery charge requirements and input power supply limitations. the LTC4020 battery charger can provide a constant-current / constant-voltage charge algorithm ( cc/cv), constant- current charging ( cc), or charging with an optimized 4 -step, 3 -stage lead-acid battery charge profile . maximum converter and battery charge currents are resistor programmable . the ic's instant-on operation ensures system load power even with a fully discharged battery. additional safety features include preconditioning for heavily discharged batteries and an integrated timer for termination and protection. a pplica t ions l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7583113 and 8405362. n wide voltage range: 4.5v to 55v input, up to 55v output (60v absolute maximums) n synchronous buck-boost dc/dc controller n li-ion and lead-acid charge algorithms n 0.5% float voltage accuracy n 5% charge current accuracy n instant-on for heavily discharged batteries n ideal diode controller provides low loss powerpath when input power is limited n input voltage regulation for high impedance input supplies and solar panel peak power operation n onboard timer for protection and termination n bad battery detection with auto-reset n ntc input for temperature qualifed charging n binary coded open-collector status pins n low profle (0.75mm) 38-pin 5mm 7mm qfn package n portable industrial and medical equipment n solar-powered systems n military communications equipment n 12v to 24v embedded automotive systems buck-boost dc/dc converter controller with powerpath battery charger accepts inputs from 4.5v to 55v and produces output voltages up to 55v 5v to 30v 6-cell lead-acid supply/charger maximum power efficiency vs v in (application circuit on page 37) LTC4020 r ntc r senseb r sensea buck-boost dc/dc converter powerpath battery charger 4020 ta01a v in v out r cs bg1 tg1 sensbot senstop sensvin bg2 tg2 v fbmax csp csn bgate vfb ntc sensgnd ltc 4020 4020fd
2 for more information www.linear.com/LTC4020 p in c on f igura t ion a bsolu t e maxi m u m r a t ings pv in , sensvin ............................................. C 0.3 to 60 v bst 1, bst 2 .................................................. C 0.3 to 66 v sw 1, sw2 ........................................................ C2 to 60 v sensvin C pv in ........................................... C0. 3 to 60 v bst 1 C sw 1, bst 2 C sw2 ............................. C 0.3 to 6v sensvin C senstop , sensbot C sensgnd .................................................... C 0.3 to 0.3 v csp , csn ..................................................... C 0.3 to 60 v csp C csn ................................................... C 0.3 to 0.3 v stat 1, stat 2, shdn ................................... C 0.3 to 60 v v fbmax , v inreg , v fb , v fbmin , bat , fbg ....... C 0.3 to 60 v mode ............................................................. C 0.3 to 6v status pin currents : sta t 1, stat 2 ...................................................... 5 ma op erating junction temperature range ( note 2) ....................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (note 1) 13 14 15 16 top view 39 sgnd uhf package 38-lead plastic qfn (5mm 7mm) 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1tg1 bst1 sgnd sensgnd sensbot senstop sensvin rt shdn v in_reg mode stat1 tg2 bst2 sgnd vc ith v fbmax i limit csout csp csn bgate bat sw1 bg1 pv in pgnd intv cc bg2 sw2 stat2 timer rng/ss ntc vfb fbg v fbmin 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w, jc = 2c/w exposed pad (pin 39) is sgnd, must be soldered to pcb lead free finish tape and reel part marking* package description temperature range LTC4020euhf#pbf LTC4020euhf#trpbf 4020 38-lead (5mm 7mm) plastic qfn C40c to 125c LTC4020iuhf#pbf LTC4020iuhf#trpbf 4020 38-lead (5mm 7mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. symbol parameter conditions min typ max units buck-boost switching converter v in operating voltage range pv in ; sensvin l 4.5 55 v uvlo v in supply uvlo (rising) v in supply uvlo hysteresis dc/dc functions enabled v in falling l 3.6 4.0 0.4 4.4 v v sensvin supply uvlo (rising) sensvin uvlo hysteresis intv cc enabled sensvin falling 3.4 0.3 v v bst supplies uvlo (rising) bst supplies uvlo hysteresis bst1 C sw1; bst2 C sw2; sw1, sw2 = 0v l 3.0 3.3 0.4 3.8 v v e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). pv in = sensvin = csp = csn = bat = 20v, shdn = 2v, c (tg1, bg1, tg2, bg2) = 1000pf, v rng/ss = 2v. o r d er i n f or m a t ion (http://www .linear.com/product/LTC4020#orderinfo) ltc 4020 4020fd 3 for more information www.linear.com/LTC4020 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). pv in = sensvin = csp = csn = bat = 20v, shdn = 2v, c (tg1, bg1, tg2, bg2) = 1000pf, v rng/ss = 2v. symbol parameter conditions min typ max units intv cc boost refresh supply voltage i load = 5ma l 4.85 5.0 5.15 v boost refresh supply dropout pv in = 4.5v; i intvcc = 5ma 4.46 v boost refresh supply short-circuit current limit v intvcc = 0v l 85 150 ma i pvin pv in operating current note 3; ith = 0v l 1.6 3 ma shutdown current v shdn = 0 l 3 6 a i sensvin sensevin operating current l 0.25 0.5 ma shutdown current v shdn = 0 l 25 60 a i senstop sensetop operating current 32.5 a shutdown current v shdn = 0 0.1 a v fbmax dc/dc converter reference charging terminated l 2.7 2.75 2.8 v shdn ic enable threshold (rising) threshold hysteresis l 1.175 1.225 100 1.275 v mv shdn pin bias current 10 na v sens dc/dc converter inductor current limit (average value) v sensvin C v senstop ; v sensgnd C v sensbot l 45 50 60 mv reverse current inhibit (average value) v ith falling (tg2 disabled) v ith rising (tg2 enabled) l 0 2 6 mv mv i limit inductor current limit programming v ilimit = 0.5v; v ilimit /v sens(max) 20 v/v i limit pin bias current l 47.5 50 52.5 a ith error amp current limit v fbmax = 0, v ith = 1.3v 8 a error amp transconductance v fbmax = 2.75v; v ith = 1.3v 95 umho vc high side current sense transconductance (v sensvin C v sensetop ) to i vc v c = 1.8v 200 umho low side current sense transconductance (v sensgnd C v sensebot ) to i vc v c = 1.8v 200 umho dc max maximum duty cycle bg2: t on ? f o l 70 80 % f o switching frequency r rt = 100k r rt = 50k r rt = 250k l 235 250 500 100 265 khz khz khz t on minimum on time bg2 l 150 250 ns t off minimum off time tg1 l 300 500 ns t tr gate drive transition time tg1, bg1, tg2, bg2 5 ns t nol gate drive non-overlap time (tg1 C sw1) to bg1, (tg2 C sw2) to bg2 75 ns ltc 4020 4020fd 4 for more information www.linear.com/LTC4020 symbol parameter conditions min typ max units battery charger v bat charger output voltage range l 55 v v fb float reference auto recharge voltage precondition threshold (rising) precondition hysteresis cc /cv charging (mode = 0v) % of float reference % of float reference l l l 2.4875 2.475 96.5 68 2.5 97.5 70 85 2.5125 2.525 98.5 72 v v % % mv absorption reference float reference bulk charge threshold (falling) precondition threshold (rising) precondition hysteresis lead-acid charging (mode = int v cc ) % of absorption reference % of absorption reference % of absorption reference l l l l 2.4875 2.475 91.5 86 68 2.5 92.5 87.5 70 85 2.5125 2.525 93.5 89 72 v v % % % mv v oltage reference cc charging (mode = - nc -) l 2.4875 2.475 2.5 2.5125 2.525 v v v in_reg input regulation reference % of float (cc/cv), safety (cc), or absorption (la) reference l 98 100 102 % v fbmin instant-on reference % of float (cc/cv) or absorption (la) reference l 84 85 86 % c/10 detection enable (rising) hysteresis (falling) 2.175 20 v mv instant-on charge current reduction threshold v csn C v bat ; note 4 0.45 v c/10 detection enable c/10 detection hysteresis v csn C v bat falling v csn C v bat rising 1.05 150 v mv charge current reduction gain v cs(max) /(v csn C v bat );note 4 C33 mv/v i batq battery bias currents with powerpath switcher disabled i csp + i csn + i bat l 9 18 a csn, csp charger current sense pin operating bias currents i csp = i csn ; charging enabled 40 a charger current sense limit voltage v csp C v csn l 47.5 50 52.5 mv charger current sense termination voltage (c/10) v csp C v csn ; mode = 0v l 3 5 7 mv charger current sense precondition voltage v csp C v csn ; v fb = 1.5 l 1.5 3 4.5 mv sense input uvlo uvlo hysteresis v csp rising (charging enabled) v csp falling (charging disabled) l 1.6 1.75 100 1.9 v mv csout offset v csp = v csn l 0.225 0.25 0.290 v gain v csout / (v csp C v csn ) l 19 20 21 v/v rng/ss current limit programming v rng/ss = 0.5v; v rng/ss /v cs(max) l 18 20 22 v/v ntc ntc range limit (high) ntc range limit (low) ntc range hysteresis v ntc rising v ntc falling % of v ntc(h,l) l l 1.30 0.27 1.35 0.3 20 1.40 0.33 v v % i ntc ntc pin bias current v ntc = 0.8v l 47.5 50 52.5 a ntc disable current intc pin current (falling) 3.5 a ntc disable current hysteresis 2 a v bgate gate clamp voltage v csn C v bgate l 7 9.5 12 v c/10 detection enable (falling) c/10 detection enable hysteresis v csn < 7v 0.425 0.125 v v e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). pv in = sensvin = csp = csn = bat = 20v, shdn = 2v, c (tg1, bg1, tg2, bg2) = 1000pf, v rng/ss = 2v. ltc 4020 4020fd 5 for more information www.linear.com/LTC4020 symbol parameter conditions min typ max units bgate bgate pull-down current charging enabled 15 a bgate pull-up current charging disabled; v csn C v bgate = 2v 15 a bgate standby pull-down current v shdn = 0v 120 a ideal diode pull-down current charging disabled; v bat C v csn = 0.5v 500 a ideal diode forward voltage v bat C v csn ; v csn measured through 100 series resistor l 5 14 20 mv timer timer high threshold 1.5 v timer low threshold 1.0 v c/10 mode threshold (rising) l 0.4 0.5 0.6 v c/10 mode hysteresis 225 mv timer source/sink current v timer = 1.25v l 8.5 10 11.5 a v stat (l) status pins enabled voltage i stat 1 = 1ma; i stat 2 = 1ma i stat 1 = 5ma; i stat 2 = 5ma l l 0.15 0.75 0.4 2.5 v v i vfbmin instant-on feedback bias current 10 na i vfb feedback pin bias current 10 na i vin_reg input regulation bias current 10 na i fbg pin current (disabled) v shdn = 0v; v fbg = 55v 10 na r ntc ntc minimum disable resistance l 250 400 k r fbg fbg resistance to sgnd i fbg = 1ma l 20 50 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). pv in = sensvin = csp = csn = bat = 20v, shdn = 2v, c (tg1, bg1, tg2, bg2) = 1000pf, v rng/ss = 2v. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC4020 is tested under pulsed load conditions such that t j t a . the LTC4020e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. the LTC4020i is guaranteed over the full C40c to 125c operating junction temperature range. the junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (pd) according to the formula t j = t a + (pd ? j a ). note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. this ic includes overtemperature protection that is intended to protect the device during momentary overload. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability . note 3: icc does not include switching currents. v bst1 = v bst2 = v intvcc and v sw1 = v sw2 = 0v for testing. note 4: see typical performance characteristics ltc 4020 4020fd 6 for more information www.linear.com/LTC4020 typical p er f or m ance c harac t eris t ics shutdown current vs temperature (i pvin + i sensvin + i senstop ) intv cc short-circuit current limit vs temperature maximum charge current (percent of programmed i csmax ) vs rng/ss voltage instant-on: maximum charge current (percent of i csmax ) vs v csnC b at i batq (i b at + i csn + i csp ) vs v b at powerpath switcher disabled i batq (i b at + i csn + i csp ) vs temperature powerpath switcher disabled v float(cc/cv) or, v absorb(lead-acid) reference vs temperature v float(lead-acid) reference vs temperature v fbmax reference vs temperature temperature (c) voltage (v) 2.80 2.79 2.78 2.77 2.76 2.75 2.74 2.73 2.72 2.71 2.70 5020 5 ?10?25?40 80 95 110 4020 g03 125 35 65 temperature (c) standby mode current (a) 50 45 40 35 30 15 25 20 60 ?40?30?20 ?10 0 10 80 90 4020 g04 50403020 70 temperature (c) intv cc current limit (ma) 155 154 153 152 151 150 149 148 147 146 145 5020 5 ?10?25?40 80 95 110 4020 g05 125 35 65 rng/ss voltage (v) 0 maximum charge current (%) 100 90 70 50 80 60 40 30 20 10 0 0.4 0.8 1.0 4020 g06 1.2 0.2 0.6 v bat (v) 0 i batq (a) 11.0 10.5 10.0 8.0 9.5 9.0 8.5 7.0 6.5 7.5 6.0 10 30 4535 40 50 4020 g08 55 5 15 2520 temperature (c) ?40 voltage (v) 2.36 2.35 2.34 2.33 2.32 2.31 2.30 2.29 2.28 2.27 2.26 2.25 20?10 80 95 110 4020 g02 125 5 35 50 ?25 65 temperature (c) ?40 voltage (v) 2.525 2.520 2.510 2.500 2.515 2.505 2.495 2.490 2.485 2.480 2.475 20 35 50 ?10 80 95 110 4020 g01 125 5?25 65 v csn?bat (v) 0 maximum charge current (%) 100 90 70 50 80 60 40 30 20 10 0 0.5 1 1.25 4020 g07 2.25 1.5 1.75 2.5 2 0.25 0.75 temperature (c) i batq (a) 11.0 10.5 10.0 9.5 8.0 9.0 8.5 60 ?40?30?20 ?10 0 10 80 90 4020 g09 50403020 70 v bat = 20v t a = 25c, unless otherwise noted. ltc 4020 4020fd 7 for more information www.linear.com/LTC4020 typical p er f or m ance c harac t eris t ics ideal diode v f vs battery voltage ideal diode v f vs temperature i intvcc (ma) 0 v intvcc (v) 4.5 4.4 4.2 4.1 4.3 4.0 10 30 40 4020 g12 50 20 25c 125c pv in = 4.5v v (csp-csn) (mv) 0 v csout (v) 1.3 1.2 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1.1 0.2 10 30 40 4020 g13 50 20 bst refresh regulator dropout intv cc vs i intvcc csout vs csp-csn switching frequency vs input voltage switching frequency vs temperature i rng/ss , i limit , i ntc , vs temperature feedback references vs input voltage intv cc vs v in v in (v) 5 feedback references (v) 2.80 2.75 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.70 2.25 1510 3530 4540 50 4020 g14 55 2520 vfbmax vfloat(cc/cv;absorb) vfloat(lead-acid) v in (v) 5 v intvcc (v) 5.10 5.08 5.04 5.02 5.00 4.98 4.96 4.94 4.92 5.06 4.90 1510 3530 4540 50 4020 g15 55 2520 i intvcc = 5ma temperature (c) ?40 i rng/ss , i limit , i ntc (a) 52.5 52.0 51.0 50.5 50.0 49.5 49.0 48.5 48.0 51.5 47.5 ?25 5 20 35 50 65 80 11095 4020 g18 125 ?10 v bat (v) 0 ideal diode v f (mv) 16.0 15.5 15.0 13.5 13.0 12.5 14.5 14.0 12.0 10 25 30 35 40 45 50 4020 g10 55 5 15 20 temperature (c) ?40 ideal diode v f (mv) 24 22 20 16 14 12 18 10 ?10 35 50 65 80 95 110 4020 g11 125 ?25 5 20 v bat = 20v t a = 25c, unless otherwise noted. v in (v) 0 switching frequency (khz) 255 254 252 251 250 249 248 247 246 253 245 10 30 40 50 4020 g16 60 20 r rt = 100k temperature (c) ?40 switching frequency (khz) 255 254 252 251 250 249 248 247 246 253 245 ?25 5 20 35 50 65 80 11095 4020 g17 125 ?10 v in = 20v r rt = 100k ltc 4020 4020fd 8 for more information www.linear.com/LTC4020 p in func t ions tg1 (pin 1): v in side (step-down) primary switch fet gate driver output. bst1 (pin 2): boosted supply rail for v in side (step-down) switch fets . connect 1f capacitor from this pin to sw1. connect 1a schottky diode cathode to this pin, anode to intv cc pin. sensgnd (pin 4): kelvin connection for pgnd used for sensbot current sense reference. sensbot ( pin 5): ground referred current sense amplifier input. inductor current is monitored via a pgnd referenced current sense resistor (r senseb ), typically in series with the source of the v in side synchronous switch fet . kelvin connect this pin to the associated sense resistor . inductor current is limited to a maximum average value (i lmax ), and corresponds to 50mv across this sense resistor during normal operation. r senseb = 0.05/i lmax set r senseb = r sensea , as described in senstop pin description. a filter capacitor (c sensb ) is typically con- nected from sensbot to sensgnd for noise reduction . c sensb ~ 1ns/r senseb see applications information section. senstop (pin 6): v in referred current sense amplifier input. inductor current is monitored via a v in referenced current sense resistor (r sensea ), typically in series with the drain of the v in side primary switch fet . kelvin con - nect this pin to the associated sense resistor. inductor current is limited to a maximum average value (i lmax ), and corresponds to 50mv across this sense resistor dur - ing normal operation. r sensea = 0.05/i lmax set r sensea = r senseb , as described in sensbot pin description. sensvin (pin 7): kelvin connection for input supply (v in ) used for senstop current sense reference. input power supply pin for most internal low current functions. typical pin bias current is 0.25ma. rt (pin 8): system oscillator frequency control pin . connect resistor (r rt ) from this pin to ground. resistor value can range from 50k (500khz) to 500k (50khz). r rt = 100k yields 250khz operating frequency. see applications information. shdn (pin 9): precision threshold shutdown pin. en - able threshold is 1.225v (rising), with 100mv of input hysteresis. when in shutdown, all charging functions are disabled and input supply current is reduced to 27.5a. typical shdn pin input bias current is 10na. v in_reg (pin 10): input voltage regulation reference . battery charge current is reduced when the voltage on this pin falls below 2.5v. connecting a resistor divider from v in to this pin enables programming of minimum operational v in voltage for the battery charging function . this is used to program the peak power voltage for a solar panel, or to help maintain a minimum voltage on a poorly regulated input supply. this pin should not be used to program minimum operational v in voltage with low impedance supplies. should the input supply begin to collapse, the LTC4020 reduces the dc/dc converter input power such that programmed minimum v in operational voltage is maintained. if the voltage regulation feature is not used, connect the v in_reg pin to v in or intv cc . typical v in_reg pin input bias current is 10na. see applications information. mode (pin 11): charger mode control pin. short this pin to ground to enable a constant-current/constant-voltage ( cc/ cv) charging algorithm. connect this pin to pin intv cc to enable a 4-step, 3-stage lead-acid charging algorithm. float this pin to force a constant-current (cc) charging function. see applications information section. s tat 1 (pin 12): open-collector status output, typically pulled up through a resistor to a supply voltage . this status pin can be pulled up to voltages as high as 55v when the pin is disabled, and can sink currents up to 1ma when logic low (<0.4v). pull down currents as high as 5ma (absolute maximum) are supported for higher current applications, such as lighting leds. if the LTC4020 is configured for a cc/cv charging algo - rithm, the stat1 pin is pulled low while battery charge currents exceed 10% of the programmed maximum (c /10). the stat 1 pin is also pulled low during ntc faults. the stat 1 pin becomes high impedance when a charge cycle ltc 4020 4020fd 9 for more information www.linear.com/LTC4020 is terminated or when charge current is below the c /10 threshold. if the LTC4020 is configured for a cc charging algorithm, the stat 1 pin is pulled low during the entire charging cycle. the stat1 pin becomes high impedance when the charge cycle is terminated. if the LTC4020 is configured for a lead-acid charging algorithm, the stat1 pin is used as a charge cycle stage indicator pin, and pulled low during the bulk and absorp - tion charging stages. the pin is high impedance during the float charging period and during ntc or bad batter y faults . see applications information section. s tat 2 (pin 13): open-collector status output, typically pulled up through a resistor to a supply voltage . this sta - tus pin can be pulled up to voltages as high as 55v when disabled , and can sink currents up to 1ma when enabled (<0.4v). pull down currents as high as 5ma (absolute maximum) are supported for higher current applications, such as lighting leds. if the LTC4020 is configured for a cc/cv charging algo - rithms, the stat2 pin is pulled low during ntc faults or after a bad battery fault occurs. if the LTC4020 is configured for a cc charging algorithms, the stat2 pin is pulled low during ntc faults. if the LTC4020 is configured for a lead-acid charging algorithm, the stat2 pin is used as a charge cycle stage indicator pin, and pulled low during the bulk and float charging stages. the pin is high impedance during the absorption charging stage and during ntc or bad bat - tery faults. see applications information section. timer (pin 14): end-of-cycle timer programming pin . if a timer based charging algorithm is desired, connect a capacitor (c timer ) from this pin to ground. if no timer functions are desired, connect this pin to ground. end-of-cycle time (in hours) is programmed with the value of c timer following the equation: t eoc = c timer ? 1.46 x 10 7 ; during cc/cv or lead-acid charging algorithms, a bad bat - tery fault is generated if the battery voltage does not reach the precondition threshold voltage within 1/8 of t eoc , or: t pre = c timer ? 1.82 x 10 6 . a 0.2 f capacitor is typically used for cc/cv charging, which generates a 2.9 hour timer t eoc , and a precondition limit time of 22 minutes. a 0.47 f capacitor is typically used for a lead-acid charger, which generates a 6.8 hour absorption stage safety timeout. rng/ss (pin 15): battery charge current programming pin. this pin allows dynamic adjustment of maximum charge current, and can be used to employ a soft-start function. setting the voltage on the rng/ss pin reduces maximum charge current from the value programmed . the maximum charge current is reduced to the fraction of programmed current ( as per the sense resistor, rcs) corresponding to the voltage set on the pin ( in volts). this pin has an effective range from 0 to 1v. for example, with 0.5v rng/ss on the pin, the maximum charge current will be reduced to 50% of the programmed value set by the sense resistor values. 50 a is sourced from the rng/ss pin, so maximum charge current can be programmed by connecting a single resistor (r rng/ss ) from rng/ss to ground, such that the voltage dropped across the resistor is equivalent to the desired pin voltage: v rng/ss = 50a ? r rng/ss soft-start functionality can be implemented by connecting a capacitor (c rng/ss ) from rng/ss to ground, such that the time required to charge the capacitor is the desired soft-start interval (t ss1 ). the voltage that corresponds to full programmed inductor current on the rng/ss pin is 1v, so the relation for this capacitor reduces to: c rng/ss = 50a ? t ss1 p in func t ions ltc 4020 4020fd 10 for more information www.linear.com/LTC4020 the rng/ss pin is pulled low during periods when charg - ing is disabled, including ntc faults, bad battery faults, and normal charge cycle termination . this allows for a graceful start after faults and when initiating new charge cycles, should soft-start functionality be implemented. both a soft-start capacitor and a programming resistor can be implemented in parallel. rng/ss voltage can also be manipulated using an active device, such as employing a pull-down transistor to dis - able charge current or to dynamically servo maximum charging current . because this pin is internally pulled to ground during fault conditions, active devices with low- impedance pull up capability cannot be used. see applications information section. ntc (pin 16): battery temperature monitor pin . connect a 10k, = 3380 ntc thermistor from this pin to ground. the ntc pin is the input to the negative temperature coef - ficient temperature monitoring circuit . this pin sources 50 a, and monitors the voltage created across the 10k thermistor. when the voltage on this pin is above 1.35v (0c) or below 0.3v (40c), charging is disabled and an ntc fault is signaled at the stat 1 and stat2 status pins. if the internal timer is being used , the timer is paused, suspending the charging cycle until the ntc fault condi - tion is relieved. there is approximately 5c of temperature hysteresis associated with each of the temperature thresh - olds. the ntc function remains enabled while thermistor resistance to ground is less than 250k. if this function is not desired, leave the ntc pin unconnected or connect a 10 k resistor from the ntc pin to ground. the ntc pin contains an internal clamp that prevents excursions above 2v, so the pin must not be pulled high with a low imped - ance source . a low impedance element can be used to pull the pin to ground. vfb (pin 17): battery voltage feedback pin . battery volt - ages are programmed through a feedback resistor divider placed from the bat pin to fbg. during cc /cv charging, the battery voltage references are: float voltage (v float ) = 2.5v trickle charge v oltage (v trk ) = 1.75v auto-restart voltage (v restart ) = 2.4375 during lead-acid charging , the battery voltage references are: absorption voltage (v absor ) = 2.5v float charge voltage (v f lt ) = 2.3125v trickle charge v oltage (v trk ) = 1.75v bulk recharge voltage (v bulk ) = 2.1875v with r fb1 connected from bat to vfb and r fb2 connected from vfb to fbg, the ratio of (r fb1 /r fb2 ) for the desired programmed battery float voltage (cc/cv charging) or absorption voltage ( lead-acid charging) follows the relation: r fb1 /r fb2 = (v float/absorb )/2.5 C 1 (v) fbg (pin 18): voltage feedback divider return. this pin contains a low impedance path to signal ground, used as the ground reference for voltage monitoring feedback resistor dividers. when v in is not present or the LTC4020 is in shutdown, this pin becomes high impedance, elimi - nating current drain from the battery associated with the feedback resistor dividers . v fbmin ( pin 19): minimum voltage feedback pin for instant- on operation. minimum dc/dc converter output voltage (v outmin ) is programmed using this pin for instant-on functionality. v outmin is programmed through a feedback resistor divider placed from the csp pin to fbg. if the battery voltage is below the voltage level programmed using this pin, the LTC4020 controls the external pow - erpath fet as a linear pass element, allowing the dc/dc converter output to achieve the minimum programmed voltage . maximum battery charge current is reduced as the voltage across the powerpath fet increases to control power dissipation. the internal v fbmin voltage reference is 2.125v. with a resistor (r min1 ) connected from csp to v fbmin , and a resistor (r min2 ) connected from v fbmin to fbg, the ratio of these resistors for the desired minimum converter output voltage follows the relation: r min1 /r min2 = (v out(min) /2.125) C 1 p in func t ions ltc 4020 4020fd 11 for more information www.linear.com/LTC4020 using the same resistor values for battery voltage pro - gramming, or r fb1 = r min1 and r fb2 = r min2 , yields an instant-on voltage that is 85% of v float (cc/ cv charging) or v absorb (lead-acid charging): v out(min) = 0.85 ? v float/absorb bat ( pin 20): battery voltage monitor pin . this pin serves as the positive reference for the LTC4020 ideal diode function. if a system load occurs that is large enough to collapse the dc/dc converter output while charging is terminated or disabled , and the battery is disconnected (powerpath fet is high impedance), the ideal diode function engages the powerpath . this function powers the system load from the battery , and modulates the powerpath fet gate such that the system output voltage is maintained with 14mv across the powerpath fet, provided the voltage drop due to r ds(on) < 14mv. this allows large loads to be accom - modated without excessive power dissipation in the body diode of the powerpath fet . bga te (pin 21): powerpath fet gate driver output. this pin is controls the multiple functions of the power - path fet. this pin is pulled low during a normal charging cycle , minimizing the fet series impedance between the dc/ dc converter output and the battery. the bgate pin is also forced low when the dc / dc converter is disabled, maintaining a low impedance connection to power the system from the battery. when bgate is pulled low , csp bgate is limited inter - nally to 9.5v, so if csp > 9.5 v, bgate is maintained by an internal clamp at csp C bgate = 9.5v. the bgate pin must be near ground or at the clamp voltage for c/10 detection to occur. if the battery voltage is lower than the instant-on threshold (see v fbmin ), bgate servos the powerpath fet imped - ance such that a voltage drop between the csn pin and the ba t pin is created while batter y charging continues. if the v csn C v bat voltage exceeds 0.4v, maximum charge current is reduced to decrease power dissipation in the powerpath fet. when the dc/dc converter is enabled, but the battery charge cycle has terminated, bgate is pulled high to disconnect the battery from the converter output . the battery is also disconnected in the same manner during ntc faults. the ideal diode function is active during these periods, however, so if a system load occurs that is larger than what the dc/dc converter can accommodate, the battery can supply the required current , and the bgate pin will be servo controlled to force a voltage drop of only 14mv across the powerpath fet. the ideal diode function is disabled during bad battery faults. if a powerpath fet is not being used, such as with a lead- acid charging application, connect a 0.1nf capacitor from bgate to csn. csn (pin 22): battery charger current sense negative input. connect this pin to the negative terminal of the battery charge current sense resistor (rcs) through a 100 resistor. connect a filter capacitor between this pin and the csp pin for ripple reduction. see applications information section. the value of the sense resistor is related to the maximum battery charge current (i csmax ): r cs = 0.05/i csmax this pin also serves as the negative reference for the LTC4020 ideal diode function (see bat). csp (pin 23): battery charger current sense positive input. connect this pin to the positive terminal of the battery charge current sense resistor (r cs ) through a 100 resistor. connect a filter capacitor between this pin and the csn pin for ripple reduction. see applications information section. the value of the sense resistor is related to the maximum battery charge current (i csmax ) such that: r cs = 0.05/i csmax csout (pin 24): current sense amplifier output and charge current monitor. connect 100pf capacitor to ground. p in func t ions ltc 4020 4020fd 12 for more information www.linear.com/LTC4020 pin output impedance is 100k, so any loading for moni - tors must be high impedance. the sense output voltage follows the relation: v csout = 0.25 + 20 ? (v csp C v csn ) csout is only active while battery charger functions are operating. csout pin voltage is pulled to 0v after charge cycle termination or during fault conditions. i limit (pin 25): switched inductor maximum current programming pin. this pin allows dynamic adjustment of dc/dc converter maximum average inductor current, and can be used to employ a soft-start function. setting the voltage on the i limit pin reduces maximum average inductor current from the value programmed. the inductor current limit is reduced to the fraction of programmed current ( as per the sense resistors) corre- sponding to the voltage set on the pin (in volts). this pin has an effective range from 0 to 1v. for example , with 0.5v on the pin, the maximum inductor current will be reduced to 50% of the programmed value set by the sense resistor values. 50 a is sourced from this pin, so maximum inductor cur - rent can be programmed by connecting a single resistor (r ilimit ) from i limit to ground, such that the voltage dropped across the resistor is equivalent to the desired pin voltage: v ilimit = 50a ? r ilimit soft-start functionality can be implemented by connecting a capacitor (c ilimit ) from i limit to ground, such that the time required to charge the capacitor is the desired soft- start interval (t ss2 ). the voltage that corresponds to full inductor current on the i limit pin is 1v, so the relation for this capacitor reduces to: c ilimit = 50a ? t ss2 i limit voltage can also be manipulated using an active device, such as employing a pull-down transistor to dis - able dc/ dc converter current or to dynamically servo maximum current. because this pin is internally pulled to ground during portions of the converter power-up cycle , active devices with low impedance pull-up capability can- not be used. v fbmax (pin 26): dc/dc converter output feedback pin. maximum dc/dc converter output voltage (v outmax ) is programmed using this pin. when a battery charge cycle is terminated or disabled, and the battery is disconnected ( powerpath fet is high impedance), the converter output will servo to this maximum voltage. the internal v fbmax voltage reference is 2.75v. with a resistor (r max1 ) connected from csp to v fbmax and a resistor (r max2 ) connected from v fbmax to fbg, the ratio of r max1 /r max2 for the desired maximum dc/ dc converter output voltage follows the relation: r max1 /r max2 = (v outmax /2.75) C 1 using the same resistor values for battery voltage pro - gramming, or r fb1 = r max1 and r fb2 = r max2 , yields an instant-on voltage that is 110% of v float ( cc/ cv charging) or v absorb (lead-acid charging): v outmax = 1.1 ? v float/absorb ith ( pin 27): dc/ dc converter voltage loop compensation pin. see applications information section for compensa - tion component selection details. vc ( pin 28): dc / dc converter current loop compensation pin. see applications information section for compensa - tion component selection details. bst2 (pin 30): boosted supply rail for v out side (step- up) switch fets. connect a 1f capacitor from this pin to sw2. connect a 1a schottky diode cathode to this pin, anode to intv cc pin. tg2 (pin 31): v out side (step-up) synchronous switch fet gate driver output. sw 2 ( pin 32): switched node for step-up switches . connect the switched inductor to this pin. connect the primary switch fet drain and synchronous switch fet source to this pin. p in func t ions ltc 4020 4020fd 13 for more information www.linear.com/LTC4020 bg2 (pin 33): v out side (step-up) primary switch fet gate driver output. intvcc (pin 34): boosted driver refresh supply. this supply is regulated to 5v and is current limited to 150ma. connect a 2.2f ceramic capacitor from this pin to pgnd. boosted supply refresh diode anodes are connected to this pin . using this pin to power external 5 v circuitry is not recommended. pgnd ( pin 35): switch high current return path for step-up primary and step-down synchronous switches. pvin (pin 36): high current input supply pin. connect 10f decoupling capacitor from this pin to pgnd. the pv in pin provides input supply current for the intv cc internal 5v linear regulator. bg1 (pin 37): v in side (step-down) synchronous switch fet gate driver output. sw1 (pin 38): switched node for step-down switches. connect the switched inductor to this pin. connect the primary switch fet source and synchronous switch fet drain to this pin. sgnd (pins 3, 29, exposed pad 39): signal ground refer - ence. connect to the output decoupling capacitor negative terminal and batter y negative terminal . the exposed pad (39) must be soldered to pcb ground (sgnd) for electrical connection and rated thermal performance. p in func t ions ltc 4020 4020fd 14 for more information www.linear.com/LTC4020 b lock diagra m dc/dc controller block diagram a switch drivers b nol pv in feedback reference (2.5v) shutdown/references pwm control counter (128 cycles) internal enable 2mv (v sens ) shdn rt voltage/current sense sensvin senstop v fbmax 2.75v 1v i limit sensbot sensgnd ith vc intv cc bst1 tg1 sw1 intv cc bg1 pgnd 2.04 2 1.225v + ? ? + + oscillator frequency set ? + ? + ? + 200 ea-c a + ? 200 ea-c b + ? 95 ea-v + ? 5k 5k gm = 10 vc buck vc boost 1v clamp/ detect s r q s r q clk 4020 bda reset 128 intv cc bg2 pgnd bst2 tg2 sw2 sgnd c d nol ltc 4020 4020fd 15 for more information www.linear.com/LTC4020 50a 0.7a 100k 1.75v v float 2.5v trickle + ? + ? + ? + ? + ? ? + ? + 240 + + ? + ? 50a v_40c 2v v ref c/10 cc/cv trickle bulk restart v_0c 270 + ? 270 + ? + 0.1v 9.3a 0.45v 14mv instant-on foldback disable charger 1.75v a (v) = 20 2.075v c/10 bulk 2.125v restart 2.4375v timer/ oscillator termination and control logic + ? + ? + ? charger enabled ideal diode instant on csout rng/ss vfb v in_reg ntc timer 4020 bdb csp csn bgate v fbmin bat ith stat1 stat2 mode fbg ic active b lock diagra m battery charger block diagram ltc 4020 4020fd 16 for more information www.linear.com/LTC4020 o pera t ion functional overview the LTC4020 is an advanced high voltage power manager and multi-chemistry battery charger designed to efficiently transfer power from a variety of sources to a system power supply rail and a battery. the LTC4020 contains a step-up/ step-down dc /dc controller that allows operation with battery and system voltages that are above, below, or equal to the input volt - age ( v in ). a precision threshold shutdown feature allows incorporation of input voltage uvlo functionality using a simple resistor divider. when in low current shutdown mode, the ic input supply bias is reduced to only 27.5a. the LTC4020 charger is programmable to produce opti - mized charging profiles for a variety of battery chemistries . the ltc 4020 can provide a constant-current/constant- voltage charge characteristic with either c/10 or timed termination for use with lithium based battery systems , a constant-current characteristic with timed termination, or an optimized 4-step, 3-stage lead-acid charge profile. maximum battery charge current is programmable using a sense resistor, and a charge current range adjust pin allows dynamic adjustment of maximum charge current. a switcher core current limit adjust pin also allows dynamic limiting of power available to the system by virtue of limit - ing maximum current in the dc/dc converter inductor. the ltc 4020 preconditions heavily discharged batteries by reducing charge current to one-fifteenth of the pro - grammed maximum. once the battery voltage climbs above an internally set threshold, the ic automatically increases maximum charging current to the full programmed value . a bad battery detection function signals a fault and suspends charging should a battery not respond to preconditioning . battery temperature is monitored using a thermistor measurement system . this feature monitors battery temperature during the charging cycle, suspending the charge cycle and signaling a fault condition if the battery temperature moves outside a safe charging range of 0c to 40c. the charge cycle automatically resumes when the temperature returns to that safe charging range. instant-on powerpath architecture ensures that an applica - tion is powered immediately after an external voltage is applied , even with a completely dead battery , by prioritiz - ing power to the application. since the controller output ( v out ) and the battery ( bat ) are sometimes decoupled, the LTC4020 includes an ideal diode controller, which guarantees that ample power is always available to v out if there is insufficient power available from the dc/dc converter. should there be no input power available (v in ), the LTC4020 makes a low impedance connection from the battery to v out though the powerpath fet. battery life is maximized during periods of input supply disconnect by reducing the LTC4020 battery standby current to less than 10a. the LTC4020 contains two digital open-collector outputs that provide charger status and signal fault conditions . these binary coded pins signal battery charging , standby or shutdown modes , battery temperature faults, and bad battery faults. dc/dc converter operation (see block diagrams) the ltc 4020 uses a proprietary average current mode dc/dc converter architecture. as shown in figure 1, when v in is higher than v out dur - ing step-down (buck) operation, switches a (driven by pin tg 1) and b (driven by pin bg1) perform the pwm required for accommodating power conversion . ideally, switch d ( driven by pin tg2) would conduct continuously and switch c ( driven by pin bg2) would stay off, making pwm switching action much like that in a synchronous buck topology. switch d uses a bootstrapped driver, however, so switch c conducts for a minimum on time of 150ns each cycle to refresh the driver and switch d is disabled to accommodate this refresh time. a 75ns non-overlap period, separates the conduction of the two switches, preventing shoot-through currents. when v in is lower than v out during step-up (boost) op - eration, switches c and d perform the pwm required for accommodating power conversion . ideally , switch a would conduct continuously and switch b would stay off, making ltc 4020 4020fd 17 for more information www.linear.com/LTC4020 o pera t ion pwm switching action much like that in a synchronous boost topology. since switch a also uses a bootstrapped drive, however, the b switch conducts for 100ns during this refresh period. a 75ns non-overlap period, separates the conduction of the two switches, preventing shoot- through currents. if v in is close to v out , the controller operates in 4-switch (buck-boost) mode, where both switch pairs pwm si - multaneously to accommodate conversion requirements. the ltc 4020 senses the dc/dc converter output voltage using a resistor divider feedback network that drives the v fbmax pin. the difference between the voltage on the v fbmax pin and an internal 2.75v reference is converted into an error current by the voltage loop transconductance amplifier (ea-v). this error current is integrated by a compensation network to produce a voltage on pin ith. the ith compensation network is designed to optimize the response of the converter to changes in load current while the converter is in regulation. at regulation, the ith pin will servo to a value that corresponds to the average inductor current of the dc/dc converter. inductor current is monitored through two like value sense resistors , placed in series with each of the v in side converter switches, a and b. the sum of these sensed currents yields a reasonably accurate continuous repre - sentation of inductor current. the voltage produced on the ith pin is translated into an offset at the input of the two current sense amplifiers . the difference between this offset voltage and the sum of the voltages is sensed on the senstop and sensbot pins, then is converted to error currents by the current sense transconductance amplifiers (ea-c a and ea-c b ). these error currents are summed and integrated by a compensation network to produce a voltage on the pin vc. this compensation network is designed to optimize the response of the converter duty cycle to required changes in inductor current. the vc pin voltage is compared to an internally generated ramp, and the output of this comparison controls the duty cycle of the chargers switches. figure 1 shows a simplified diagram of the four power switches and their connections to the ic, inductor, v in , v out , ground, and current sense elements. figure 1. converter switch diagram reverse current protection is accomplished through dis- abling the v out side synchronous switch (d) during initial power-up, when the converter is in step-up duty cycle limit, and when ith falls to a voltage that corresponds to <1/25 of programmed i lmax . once these conditions subside, the d switch remains disabled for an additional 128 clock cycles. figure 2. operating regions vs duty cycle (dc) a b v out v in r senseb tg2 sw2 sw1 bg2 tg1 bg1 sensebot sensetop d b * *optional d d * d c 4020 f01 r sensea dc max (boost) dc max (buck) dc min (boost) dc min (buck) 4020 f02 c/d pwm ? a min off, b min on 4-switch pwm a/b pwm ? c min on, d min off ltc 4020 4020fd 18 for more information www.linear.com/LTC4020 o pera t ion battery charger operation (see block diagrams) during the majority of a normal batter y charge cycle , the LTC4020 makes a low impedance connection between the battery and the dc /dc converter output through the powerpath fet, as in figure 3. this pfet is controlled by the LTC4020 through modulation of the bgate pin , which is connected to the fet gate. when charging is disabled, the fet is disabled, disconnecting the battery from the converter output by pulling the gate of the powerpath fet high via the bgate pin . the converter output is regulated by v fbmax while the fet is disabled. when normal charger operation resumes , the gate is pulled low . as the bgate pin is a slow-moving node, c/10 detection is disabled until the bgate pin approaches its normal operating voltage , which prevents premature c/10 detection during reconnection of the battery . the slow movement of bgate can also cause the converter output to regulate to v fbmax for a short time during start-up until the fet is enabled. this fet is also linearly controlled during low battery conditions to enable the instant-on function, where the converter output can be separated from a heavily discharged battery to power the rest of the system before the battery voltage responds to charging. c/10 detection is also disabled when the charger is operating in instant-on mode. this fet is also automati - cally configured as a 14mv ideal diode, which provides a low loss path from the batter y to the output when system loads require power from the battery while the battery is disconnected from the converter output. the battery charger takes control of the dc /dc converter operation by modulating the ith pin voltage in response to sensed battery charge current , battery voltage, and input voltage. the converter thus provides exactly the amount of power required to satisfy both the system load and battery charger requirements. battery charge current is monitored via an external sense resistor connected to the pins csp and csn. the voltage across this resistor is amplified internally by a factor of 20, which is output onto pin csout. this output voltage rides on top of a constant 250mv offset. the csout pin voltage drives an internal transconductance amplifier that servos the dc /dc converters ith pin voltage in response to the current requirements of a charging battery . csout voltage is also used internally as a charge current monitor to detect 19 for more information www.linear.com/LTC4020 o pera t ion use of the timer function also enables bad battery detection during cc/cv or lead-acid charging. this fault condition is achieved if the battery does not respond to preconditioning (v fb < 1.75v), such that the charger remains in (or enters) precondition mode after one-eighth of the programmed t eoc time. a bad battery fault halts the charging cycle, and the fault condition is reported on the status pins. cc/cv charging overview (mode = 0v) to program the LTC4020 for cc/cv charging, connect the mode pin to ground . this mode is commonly used for li-ion, li-polymer, and lifepo 4 battery charging. if the voltage on the vfb pin is below 1.75 v, the LTC4020 en - gages precondition mode, which provides low level charge currents to gently increase voltage on heavily discharged batteries. during preconditioning, the maximum charge current is reduced to one-fifteenth of the programmed value as set by r cs , the battery charge current program- ming resistor. full charge current capability is restored once the voltage on vfb rises above 1.75v. full charge current capability remains until the vfb pin approaches the 2.5 v float voltage. this is the constant-current (cc) portion of the charge cycle. when the voltage on the vfb pin approaches the 2.5v float voltage, the charger transitions into constant-voltage (cv) mode, and charge current is reduced from the maxi - mum programmed value . if timer termination is used, the safety timer period starts when cv mode is initiated , and the charge cycle will terminate when the timer achieves end-of-cycle (t eoc ). this timer is typically programmed to achieve t eoc in three hours, but can be configured for any amount of time by setting an appropriate timing capacitor value (c timer ). during cv mode , the required charge current is steadily reduced as the battery voltage is maintained such that the voltage on the vfb pin remains close to 2.5v. if the char - ger is configured for c/10 termination, when the battery charge current falls below one-tenth of the programmed maximum current ( 20 for more information www.linear.com/LTC4020 o pera t ion as the bulk charging stage completes and the voltage on the vfb pin rises to approach 2.5v, the charger transi - tions into the absorption stage, which is the 2nd stage of 3 -stage batter y charging. during the absorption stage, the required charge current is steadily reduced as the battery voltage approaches the absorption voltage . this is a constant-voltage charging stage, as the battery voltage is maintained such that the vfb pin remains close to the 2.5v absorption reference voltage. it is during this stage that the battery stored charge increases to 100% capac - ity. the 2.5v absorption reference typically corresponds to 14.4v for a 6-cell batter y. when the absorption stage charge current is reduced to one-tenth of the programmed maximum current, the charger will initiate the third stage in the charge profile , the float charging stage. the safety timer can be used with a lead-acid charger to limit the duration of the absorption stage of the charging profile . the timer is initiated at the start of the absorption stage, and forces the charger into float if the charge current does not fall to the required one-tenth of the programmed maximum current during the absorption stage before the timer reaches t eoc . a 0.47f capacitor on the timer pin is typically used, which generates a 6.8 hour absorption stage safety timeout. once the float charging stage is initiated, the battery reference voltage is reduced to 92.5% of the absorption voltage, or 2.3125v. the battery voltage is maintained at a voltage corresponding to this reference voltage, and maximum charge current is reduced to one-fifteenth of the programmed maximum. this level corresponds to 13.3v for a 6-cell battery. once float charging is achieved, the LTC4020 charger re - mains active and will attempt to maintain the float voltage on the batter y indefinitely . during float charging, if a load on the battery exceeds the maintenance charge current of one-fifteenth of the programmed maximum, the bat - tery voltage will begin to discharge . if a load discharges the batter y such that the voltage on vfb falls to 2.1875v, corresponding to 12.6v for a 6 -cell battery, the LTC4020 restarts the full 3 -stage charging cycle by reinitiating the bulk charging stage. bulk charging is engaged by resetting the internal vfb reference to the 2.5v absorption voltage reference and increasing the charge current capability to the programmed maximum. typical lead-acid charge cycle voltages (12v system) precondition 10.1v absorption 14.4v float 13.3v bulk restart 12.6v cc charging overview (mode = nc) to program the LTC4020 for cc charging, leave the mode pin unconnected. this mode can be used for charging nicd and nimh batteries, supercap charging, or in any other application where a timed current source is desired . cc mode can also be used when the voltage dependent precondition mode is not desired. in cc mode, the LTC4020 will maintain full programmed charge current capability for the duration of the timer period. the trickle charge function is disabled, although maximum charge current will be reduced during lower deck operation if there is excessive voltage (>0.3v) imposed across the powerpath fet. the charger will terminate the charge cycle and the powerpath fet will become high- impedance once timer eoc is reached. while the charge cycle is designed to be voltage inde - pendent, a maximum v bat voltage can be programmed corresponding to vfb = 2.5v, allowing constant-voltage functionality at that level if desired. once the timer reaches t eoc and the charge cycle ter - minates, input power or shdn must be cycled to initiate another charge cycle . if the timer function is disabled (timer = 0v), the current source function remains active indefinitely. note: for nickel-chemistry batteries (e.g. nicd or nimh), the possibility of overcharging must be considered . a typical method is to charge with low currents for a long period of time . nicd and nimh batteries can absorb a c/300 charge rate indefinitely. shorter duration charging is possible using a timed current source charge algorithm . it is recommended to ensure a depleted battery before charging, then subsequently charge the battery to no more than 125% capacity. for example, a depleted 2000mah nimh battery is charged with 2.5a for one hour. ltc 4020 4020fd 21 for more information www.linear.com/LTC4020 dc/dc converter section output voltage programming the LTC4020 dc/dc converter maximum output volt - age, or voltage safety limit, is set by an external feedback resistive divider, providing feedback to the v fbmax pin. this divider sets the output voltage that the converter will servo to when the powerpath fet is high impedance , which occurs after charge cycle termination or during a charge cycle fault. a pplica t ions i n f or m a t ion pgnd. both nodes on the sense resistor must be kelvin connected to the ic, via the pins sensbot and sensgnd. both of these sense resistors must be of equal value , and that value programs the switched inductor maximum average current in the dc/dc converter inductor (i lmax ) such that: r sensea =r senseb = 0.05 i lmax when the converter is stepping down, or operating in buck mode, the inductor current will be roughly equivalent to the converter output current. input supply current (i in ) will be less than the inductor current (i l ), such that: i l ~i in ? v in v out ? ? ? ? when the converter is stepping up, or operating in boost mode, the inductor current will be roughly equivalent to the converter input current. inductor current (i l ) will be greater than output current (i out ), such that: i l ~i out ? v out v in ? ? ? ? overcurrent detection the LTC4020 also contains an overcurrent detection circuit that monitors the low side current sense resistor, or sensbotCsensgnd input. should that circuit detect a voltage on that input that is less than C150mv or greater than 100mv, or roughly 3x the maximum average current, all of the switches are disabled for four (4) clock cycles. parasitic inductances on non-ideal layouts and or body- diode commutation charge can cause voltage spikes across the sense resistor at the beginning of synchronous fet conduction. the LTC4020 overcurrent circuitry is somewhat resistant to these leading edge spikes but , in some cases, the overcurrent circuit can be prematurely triggered. this is identified by the repeated 4 -cycle switch off-time that occurs should premature triggering occur. placing a ceramic capacitor across the sensbotC sensgnd input pins near the ic will generally eliminate figure 4. v out safety limit programming the resultant feedback signal is compared with the internal 2.75 v voltage reference by the converter error amplifier. the output voltage is given by the equation: v out = 2.75v ? 1+ r max1 r max2 ? ? ? ? where r max1 and r max2 are defined as in figure 4. the values for r max1 and r max2 are typically the same as those used for the divider that programs battery voltage (to the vfb pin; see battery charger section), to yield a dc/dc converter maximum regulation voltage, or safety limit, that is 10% higher than the battery charge voltage. r sensea , r senseb : dc/dc converter current programming the LTC4020 performs inductor current sensing via two resistors connected in series with the v in side switches (see figure 1). the high side sense resistor (r sensea ) is connected between v in and the drain of the top side switch fet (a). both nodes on the sense resistor must be kelvin connected to the ic via the pins sensvin and senstop. likewise, the low side sense resistor (r senseb ) is connected between the source of the bottom side switch fet (b) and 4020 f04 v out r max1 r max2 v fbmax LTC4020 ltc 4020 4020fd 22 for more information www.linear.com/LTC4020 premature triggering by high pass filtering the current sense signal. setting the of the effective filter in the range of 1 ns is generally sufficient to shunt errant signals, such that: c sensb ~ 1ns r senseb programming switching frequency the rt frequency adjust pin allows the user to program the LTC4020 dc/dc converter operating frequency from 50khz to 500khz. higher frequency operation is desirable for smaller ex - ternal inductor and capacitor values, but at the expense of increased switching losses and higher gate drive cur - rents. higher frequencies may also not allow sufficiently high or low duty cycle operation due to minimum on /off time constraints. lower operating frequencies require larger external component values, but result in reduced switching losses yielding higher conversion efficiencies. operating frequency (f o ) is set by choosing an appropriate frequency setting resistor (r rt ), connected from the rt pin to ground. this resistor is required for operation; do not leave this pin open. for a desired operating frequency, r rt follows the relation: r rt = 100k ? f o 250khz ? ? ? ? ? 1.0695 input supply decoupling the LTC4020 is typically biased directly from the charger input supply through the pv in and sensvin pins. this supply provides large switched currents, so a high quality, low esr decoupling capacitor is recommended to mini - mize voltage glitches on the v in supply. placing a smaller ceramic capacitor (0.1 f to 10f) close to the ic in parallel with the input decoupling capacitor is also recommended for high frequency noise reduction. the sensvin pin is a kelvin connection from the v in supply at the primary v in side switch fet (a); separate decoupling for that pin is not recommended. the charger input supply decoupling capacitor (c vin ) absorbs all input switching ripple current in the charger, so it must have an adequate ripple current rating. rms ripple current (i cvin(rms) ) is highest during step down operation, and follows the relation: i cvin(rms) ~i max ? dc ? 1 dc C 1 , which has a maximum at dc = 0.5, or v in = 2 ? v out , where: i cvin(rms) = i max 2 the simple worst-case of ? ? i max is commonly used for design, where i max is the programmed inductor current limit. bulk capacitance (c in(bulk) ) is a function of desired input ripple voltage (v in ). for step-down operation, c in(bulk) follows the relation: c in(bulk) i max ? v out(max) v in(min) ? 1 v in ? f o , where f o is the operating frequency, v out(max) is the dc/ dc converter maximum output voltage and v in(min) is the regulation voltage corresponding to 2.5v on v in_reg . if the input regulation feature is not being used , use the minimum expected input operating voltage. if an application does not require step-down operation , during step-up operation, input ripple current is equivalent to inductor ripple current (i max ), so c in(bulk) follows the relation: c in(bulk) = i max v in ? f o figure 5. rt vs operating frequency a pplica t ions i n f or m a t ion rt (k ) 50 operating frequency (khz) 600 500 400 300 200 100 0 250 150 350 400 450 4020 f05 500 200 100 300 ltc 4020 4020fd 23 for more information www.linear.com/LTC4020 i limit pin maximum average inductor current can be dynami - cally adjusted using the i limit pin as described in the pin description section. active servos can also be used to impose voltages on the i limit pin , provided they can only sink current . active circuits that source current cannot be used to drive the i limit pin. using whichever relation yields the largest inductor value for l min : if v in > v out (step-down conversion): l min = v out ? 1? v out / v in(max) ? ? ? ? ( ) f o ? ?i max ? i max if v in < v out (step-up conversion): l min = v in ? 1? v in / v out(max) ? ? ? ? ( ) f o ? ?i max ? i max for step-down conversion, use the maximum expected operating voltage for v in(max) . if the expected v out operating range (typically from v fbmin = 2.125 v to v fbmax = 2.75 v) includes v in(max) /2, use that value for v out . if the entire operating range is below v in(max) /2, use the value corresponding to v fbmax = 2.75v. if the entire operating range is above v in(max) /2, use the value corresponding to v fbmin = 2.125v. for step-up conversion, use the maximum output volt - age ( typically corresponding to pin v fbmax = 2.75v) for v out(max ). if the expected v in operating range includes v out(max) /2, use that value for v in . if the entire input operating range is below v out(max) /2, use the maximum operating voltage for v in . if the entire input operating range is above v out(max) /2, use the minimum input operating voltage for v in . magnetics vendors typically specify inductors with maximum rms and saturation current ratings. select an inductor that has a saturation current rating at or above 1.25 ? i max , and an rms rating above i max . output decoupling during periods when the LTC4020 dc/ dc converter output is not connected to the battery through the powerpath fet, the system load is driven directly by the converter. the converter creates large switched currents, so a high quality, low esr decoupling capacitor is recommended to minimize voltage glitches on the v out supply. placing a smaller ceramic decoupling capacitor (0.1f to 10f) in parallel with the output decoupling capacitor is also recommended for high frequency noise reduction. the v out decoupling capacitor (c vout ) absorbs the majority of a pplica t ions i n f or m a t ion figure 6. using the i limit pin for digital control of maximum average inductor current figure 7. driving the i limit pin with a current sink active servo amplifier 4020 f06 10k logic high = half current i limit LTC4020 4020 f06 servo reference i limit LTC4020 ? + inductor selection the primary criterion for inductor value selection in an LTC4020 charger is the ripple current created in that induc - tor. once the inductance value is determined, an inductor must also have a saturation current equal to or exceeding the maximum peak current in the inductor. an inductor value (l) is calculated given the maximum desired amount of ripple current (i max ). maximum inductor ripple current should generally be in the range of 0.2 to 0.5 (as a fraction of maximum average inductor current, i max ). when stepping down, ripple current gets larger with increased v in , and is maximized when v out = v in /2. when stepping up, ripple current gets larger with increased v out , and is maximized when v in = v out /2. the inductor value must be chosen using the greatest expected operational difference between these values. a minimum inductor value for a given maximum ripple current and operating frequency (f o ) can be determined ltc 4020 4020fd 24 for more information www.linear.com/LTC4020 the converter ripple current, so it must have an adequate ripple current rating. rms ripple current (i rms ) is highest during step up operation, and follows the relation: i rms ~i max ? dc ? 1 dc C 1 , having a maximum at dc = 0.5, or v out = 2 ? v in , where: i cvout(rms) = i max 2 . the simple worst-case of ? ? i max is commonly used for design, where i max is the programmed inductor current limit. bulk capacitance is a function of desired output ripple voltage (v out ), and follows the relations: for step-up operation: c out(bulk) i max ? v out(max) C v in(min) v out(max) ? 1 v out ? f o , where v out(max) is the dc/dc converter safety limit, and v in(min) is the v in regulation threshold. if the v in regula- tion feature is not being used , use the minimum expected operating voltage . for step-down operation , output ripple current is equivalent to inductor ripple current ( i max ), so c out(bulk) follows the relation: c out(bulk) i max v out ? f o , switch fet selection the LTC4020 requires four external n-channel power mosfets, as shown in figure 1. specified parameters used for power mosfet selection are: breakdown voltage (v br( dss) ), threshold voltage (v gs(th) ), on-resistance (r ds(on) ), reverse transfer ca - pacitance ( c rss ), and maximum inductor current (i lmax ). the drive voltage is set by the intv cc supply pin, which is typically 5v. consequently, logic-level threshold mosfets must be used in LTC4020 applications. transition losses (p tr ): during maximum power opera- tion, all 4 switches change state once per oscillator cycle, so the maximum switching transient power losses (p tr ) remain constant over condition. p tr(a, b) (k)(v in ) 2 (i lmax )(c rss )(f o ) p tr(c, d) (k)(v out ) 2 (i lmax )(c rss )(f o ) p tr(a, b) is the transition loss for the v in side switch fets a and b, and p tr(c,d) is the transition loss for v out side switch fets c and d , with the switch fets designated as in figure 1. the constant k, which accounts for the loss caused by reverse recovery current , is inversely propor - tional to the gate drive current and has a empirical value approximated by k = 1 in LTC4020 applications. i lmax is the converter maximum inductor current as programmed by the two sense resistors. conductive losses (p on ): conductive losses are propor - tional to switch duty cycle. the average conductive losses in a switch at maximum inductor current (i lmax )is: p on = i lmax 2 ? t ? r ds(on) ? (t on ? f o ) where t is a normalization factor (unity at 25c) ac - counting for the significant variation in on-resistance with temperature . for a maximum junction temperature of 125c, using a value of t = 1.5 is reasonable. if v in > v out (step-down conversion): p on(a) = i lmax 2 ? t ? r ds(on(a)) ? (v out /v in ) p on(b) = i lmax 2 ? t ? r ds(on(b)) ? (1 C v out /v in ) p on(c+d) = i lmax 2 ? t ? r ds(on(c, d)) if v in < v out (step-up conversion): p on(a+b) = i lmax 2 ? t ? r ds(on(a, b)) p on(c) = i lmax 2 ? t ? r ds(on(c)) ? (1 C v in /v out ) p on(d) = i lmax 2 ? t ? r ds(on(d)) ? (v in /v out ) optional schottky diode (db, dd) selection schottky diodes can be placed in parallel with the syn - chronous fets b and d , as shown in figure 1 as db and dd . these diodes conduct during the dead time between the conduction of the power mosfet switches and are intended to prevent the body diode of synchronous switches from storing charge. a pplica t ions i n f or m a t ion ltc 4020 4020fd 25 for more information www.linear.com/LTC4020 to maximize effectiveness of the diodes , the inductance between the switches and the synchronous switches must be minimized, so the diodes should be placed adjacent to their corresponding fet switch. the dd diode also reduces power dissipation in the d switch during periods of reverse current inhibit operation, during which time the d switch is disabled. load currents are low during reverse inhibit, and diode db only conducts during switch dead times, so both can have current ratings well below the dc/dc converter inductor current maximum. typically , a diode with an average current rating at or above one-tenth of i lmax is adequate, provided the diode has an instantaneous current rating that exceeds the maximum inductor current, or i lmax + ? i max . db reverse voltage rating must exceed v in . dd reverse voltage rating must exceed v out . intv cc ldo output, and bst1 and bst2 supplies power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. an internal 5 v low dropout regulator (ldo) supplies intv cc power from the pv in pin. intv cc is decoupled to pgnd using a 2.2f ceramic capacitor. the bst1 and bst2 bootstrapped supply pins power internal high side fet gate drivers, which output to pins tg1 and tg2. bst1 provides switch gate drive above the input power supply voltage for switch fet a, and bst2 provides switch gate drive above the output power supply voltage for switch fet d, as designated in figure 1. these boosted supply pins allows the use of nfet switches for increased conversion efficiency. these bootstrapped sup - plies are regenerated through external schottky diodes from the intv cc pin. connect two low leakage 1a schottky diode anodes to the intv cc pin. connect one schottky cathode to the bst1 pin. this diode must be rated for reverse voltage standoff exceeding the maximum input supply voltage. connect the other diode cathode to the bst2 pin. this diode must be rated for reverse voltage standoff exceeding the converter safety limit output, v out(max) . connect a ceramic capacitor from the bst1 pin to the sw1 pin and another from bst2 pin to the sw2 pin. the value of these two capacitors should be at least 50 times greater than the equivalent total gate capacitance of the corresponding switch fet . total fet gate charge (q g(tot) ) is typically specified at a specific gate-source voltage (v gs(q) ). using those parameters, the required boost capacitor values (c bst ) follow the relation: c bst > 50 ? q g(tot) /v gs(q) c bst = 1f is typically adequate for most applications. during low load operation , start-up , and nonoverlap periods, inductor current is conducted by the silicon body diode of the synchronous fet. this diode stores a significant amount of charge, so when the primary switch turns on for the next switch cycle, reverse recovery current is conducted by the main switch to discharge this diode. the resultant short-duration current spike can be orders of magnitude greater than the inductor current itself, resulting in an extremely fast dv/dt on the switched node. conse - quently, parasitic inductance associated with the switch fet packaging and / or less-than-ideal layout can induce a voltage spike of 10 or more volts at the leading edge of a switching cycle. this can be particularly problematic on the step-up side of the inductor, as these voltage spikes are negative, and can cause a build-up of voltage on the bst2-sw2 capacitor. this would generally occur when the step-up synchronous switch (d) is disabled, such as during low load operation and during start-up. if voltage build-up on the boosted supply proves excessive , it could potentially violate absolute maximum voltage ratings of the ic and cause damage. this effect can be greatly reduced by implementing a schottky diode across the step-up synchronous fet, shown as d d in figure 1, which reduces reverse recovery charge in the synchronous fet body diode. a low current 6v zener (0.1a) in parallel with the bst2-sw2 capacitor will also effectively shunt any errant charge and prevent excessive voltage build-up. external power for bst1 and bst2 supplies power for the top and bottom mosfet drivers can be supplied by an external supply, provided that a precision 5v supply is available (5%). the intv cc internal supply is a linear regulator, which transfers current from the v in pin. as such, power dis- sipation can be excessive with high v in pin voltages and/ a pplica t ions i n f or m a t ion ltc 4020 4020fd 26 for more information www.linear.com/LTC4020 figure 9. connection of external 5v regulator for reduced internal power dissipation figure 8. intv cc pass element soa (safe operating area) q g(tot)abcd ? f o (ma) 0 v in (v) 60 50 40 30 20 10 0 40 20 60 70 80 4020 f08 90 30 10 50 soa 4020 f09 LTC4020 v in sensvin intv cc v in v in (5v) 5v out or large gate drive requirements. the power dissipation in the linear pass element (p intvcc ) is: p intvcc = (v in C 5v) ? q g(tot)abcd ? f o , where q g(tot)abcd is the sum of all four switch total gate charges, and f o is the LTC4020 switching frequency. in this configuration, the intv cc pin cannot collapse when the LTC4020 is in shutdown. as a result of the pin bias being maintained during shutdown, current will flow into the intv cc pin, increasing input supply current. the total shutdown current flowing into the intv cc pin in this configuration is approximately 150a. battery charger section battery charge voltage programming the LTC4020 uses an external feedback resistive divider from the bat pin to ground to program battery voltages . this divider provides feedback to the vfb pin, and sets the final voltage that the battery charger will achieve at the end of a charge cycle . the feedback reference of 2.5v corresponds to the battery float voltage during cc /cv mode charging (mode = 0v). a pplica t ions i n f or m a t ion figure 11. battery voltage programming figure 10. connection of low-voltage input supply if desired operation places the internal 5v regulator out of the allowable soa region, deriving gate drive power externally is required. for driving the LTC4020 with an external 5v regulator, connect the pv in and intv cc pins to that regulator output as shown in figure 9. the sensvin pin remains connected to the input supply. 4020 f10 LTC4020 v in sensvin intv cc v in (4.5v to 5.5v) 4020 f11 r fb1 (battery) r fb2 vfb vbat LTC4020 for operation with tightly regulated low voltage input sup - plies (4.5 v to 5.5v), the LTC4020 internal gate drivers and bst refresh functions can be powered directly by the input supply, eliminating the requirement for a 5v regulator to supply the intv cc pin. connect the input supply to the pv in , intv cc , and sensvin pins, as shown in figure 10. the resultant feedback signal is compared with the internal 2.5v voltage reference by the converter error amplifier. the output voltage is given by the equation: v (float(cc/cv) = 2.5v 1+ r fb1 r fb2 ? ? ? ? where r fb1 and r fb2 are defined as in figure 11. if charging in cc mode (mode = -nc- ), r fb1 and r fb2 corresponding to v fb = 2.5 v programs a maximum v bat voltage, if constant-voltage functionality at that level if desired. ltc 4020 4020fd 27 for more information www.linear.com/LTC4020 during lead-acid charging (mode = intv cc ), the absorption mode voltage corresponds to 2.5v on the v fb pin. battery float voltage ( maintenance) corresponds to 2.3125 v on the vfb pin, or 92.5% of the absorption voltage. these volt- ages typically correspond to 14.4v and 13.3v respectively for a 6-cell (12v) batter y. the values for r fb1 and r fb2 are typically the same as those used for the divider that programs the converter safety limit (converter output to the v fbmax pin; see dc/dc converter section), which yields a dc/dc converter maximum regulation voltage, or safety limit, that is 10% higher than the maximum batter y charge voltage. common battery types: normalized r fb1 resistor values (r fb2 = 1) battery type voltage r fb1 1-cell lifepo 4 3.6v float 0.44 1-cell li-ion 4.2v float 0.68 2-cell lifepo 4 7.2v float 1.88 2-cell li-ion 8.4v float 2.36 6-cell lead-acid 12v battery 4.76 3-cell lifepo 4 10.8v float 3.32 3-cell li-ion 12.6v float 4.04 4-cell lifepo 4 14.4v float 4.76 6-cell lifepo 4 21.6v float 7.64 12-cell lead-acid 24v battery 10.52 r cs : battery charge current programming the LTC4020 senses battery charge current using a sense resistor that is connected between the csp and csn pins. maximum average battery charge current (i csmax ) is programmed by setting the value of this current sense resistor. the resistor value is selected so the desired maximum charge current through that sense resistor creates a 50mv drop, or: r cs = 0.05v i csmax for example , for a maximum average charge current of 5a, use a 0.01 sense resistor. powerpath fet function and instant-on the LTC4020 controls an external pmos with its gate connected to the bgate pin . this powerpath fet controls current flow to and from the battery. during a normal battery charge cycle , the bgate pin is pulled low ( clamped at v gs = 9.5v), which operates the fet as a low impedance connection from the dc/dc converter output to the battery , effectively shorting the battery to the converter output. this minimizes power dissipation from charge current passing thorough the fet. when there is no v in power or when the ic is in shutdown , LTC4020 connects the battery to the converter output by holding the bgate pin low , again effectively shorting the battery to the converter output. this minimizes power dissipation while the output is powered by the battery. the LTC4020 controls the powerpath fet to perform instant-on operation when a charge cycle is initiated into a heavily discharged battery . if the battery voltage is below a programmed minimum operational output volt - age, corresponding to v fbmin = 2.125v, the powerpath fet is configured as a linear regulator, allowing the dc/ dc converter output to rise above the battery voltage while still providing charge current into the battery . during instant-on operation, the bga te pin is driven by the LTC4020 to maintain the minimum programmed voltage on the powerpath fet source , the fet acting as a high impedance current source , providing charge current to the battery, independent of the battery voltage. a pplica t ions i n f or m a t ion figure 12. instant-on dc/dc converter output vs battery voltage characteristics v bat (v) 4020 f12 v out v fbmin = 2.125v v bat ltc 4020 4020fd 28 for more information www.linear.com/LTC4020 figure 13. v out instant-on programming figure 14. instant-on charger current sense limit reduction the resultant feedback signal is compared with the internal 2.125 v voltage reference by a dedicated instant-on error amplifier, the output of which servos the bgate pin. the output voltage is given by the equation: v out = 2.125v 1+ r min1 r min2 ? ? ? ? where r min1 and r min2 are defined as in figure 13. when the dc/dc converter is operating, but the battery charger is not in a charging cycle, the powerpath fet is automatically configured as an ideal diode between the bat pin (anode) and the csn pin (cathode). the ideal diode function allows the battery to remain disconnected from the converter output while the converter is supplying power, but also allows the battery to be efficiently engaged for ad - ditional power should a load exceed the dc/dc converters capability. this ideal diode circuit regulates the external fet to achieve low loss conduction, maintaining a voltage drop of 14 mv across from the bat pin to the csn pin, provided the battery current load though the ideal diode does not exceed 14mv/r ds(on) . with larger currents, the fet will behave like a fixed value resistor equal to r ds(on) . in certain applications, the powerpath function is not required. for example, lead-acid chargers do not termi - nate ( they remain in float charging mode indefinitely ), so the battery need never be disconnected from the output, provided the instant-on feature is not desired. the powerpath fet can be eliminated in these applica - tions by tying the csn side of the sense resistor to bat , connecting v fbmin to ground , and connecting a 100pf capacitor from the bgate pin to csn . see typical ap - plication circuits section. rng /ss: dynamic current limit adjust maximum charge current can be dynamically adjusted using the rng /ss pin as described in the pin description section. active servos can also be used to impose voltages on the rng/ss pin, provided they can only sink current. active circuits that source current cannot be used to drive the rng/ss pin. a pplica t ions i n f or m a t ion figure 15. using the rng/ss pin for digital control of maximum charge current 4020 f15 10k logic high = half current rng/ss LTC4020 4020 f13 v out r min1 r min2 v fbmin LTC4020 the values for r min1 and r min2 are typically the same as those used for the divider that programs battery voltage (to the vfb pin; see battery charger section), to yield a dc/dc converter minimum operational regulation voltage corresponding to 85% of the battery charge voltage. during instant-on operation, if the drain-to-source voltage across the powerpath fet (v csn C v bat ) exceeds 0.45v, the maximum charge current is automatically reduced. maximum charge current is reduced linearly across the range of 0.45v < v csn C v bat < 1.95 v to one-fifteenth of the current programmed by the battery charger sense resistor, rcs. this reduction in charge current helps to prevent excessive power dissipation in the powerpath fet. v csn?bat (v) 0 maximum charge current (%) 100 90 70 50 80 60 40 30 20 10 0 0.5 1 1.25 4020 f14 2.25 1.5 1.75 2.5 2 0.25 0.75 ltc 4020 4020fd 29 for more information www.linear.com/LTC4020 rng/ss: soft-start soft-start functionality is also supported by the rng/ss pin. 50 a is sourced from the rng /ss pin, so connect - ing a capacitor from the rng/ss pin to ground (c rng/ss ) creates a linear voltage ramp. the maximum charge current follows this voltage , thus increasing the charge current capability from zero to the full programmed value as the capacitor gets charged from 0 to 1v. the value of c rng/ss is calculated based on the desired time to full current (t ss ) following the relation: c rng/ss = 50a ? t ss the rng/ss pin is pulled to ground internally when charg - ing is terminated so each new charging cycle begins with a soft-start cycle. rng/ ss is also pulled to ground during bad battery and ntc fault conditions. status pins the LTC4020 reports charger status through two open collector outputs, the stat1 and stat2 pins. these pins can accept voltages as high as 55v when disabled, and can sink up to 5ma when enabled. if the LTC4020 is configured for a cc/cv charging algo - rithm, the stat1 pin is pulled low while battery charge currents exceed 10% of the programmed maximum (c /10). the stat 1 pin is also pulled low during ntc faults. the stat 2 pin is pulled low during ntc faults or after a bad battery fault occurs . the stat1 pin becomes high imped - ance when a charge cycle is terminated or when charge current is below the c /10 threshold, and the stat2 pin remains high impedance if no fault conditions are present . if the LTC4020 is configured for a cc charging algorithm, the stat 1 pin is pulled low during the entire charging cycle, and the stat2 pin is pulled low during ntc faults. the stat 1 pin becomes high impedance when the charge cycle is terminated. if the LTC4020 is configured for a lead-acid charging algorithm, the stat1 and stat2 pins are used as charge cycle stage indicator pins. the stat1 pin is pulled low during the bulk and absorption charging stages and is high impedance during the float charging period and during ntc or bad battery faults . the stat2 pin is pulled low during bulk and float charging stages, and is high impedance during the absorption charging stage and during ntc or bad battery faults. the stat 1 and stat2 status pins are binary coded, and signal following the table below , where on indicates pin pulled low, and off indicates pin high impedance: a pplica t ions i n f or m a t ion status pins state s tat 1 s t at 2 cc/cv (mode = 0v) lead-acid (mode = intv cc ) cc (mode = -nc-) off off not charging standby or shutdown mode, i cs < c/10 not charging ntc/ bad battery fault or shutdown not charging standby or shutdown mode, i cs < c/10 off on bad battery fault float charge not used on off charging cycle ok: trickle charge or i cs > c/10 absorption charge charge cycle ok on on ntc fault bulk charge ntc fault figure 17. using the rng/ss pin for soft-start 4020 f17 c rng/ss rng/ss LTC4020 figure 16. driving the rng/ss pin with a current sink active servo amplifier 4020 f16 servo reference rng/ss LTC4020 ? + ltc 4020 4020fd 30 for more information www.linear.com/LTC4020 timer: c/10 termination the LTC4020 supports a low current based termination scheme. this termination mode is engaged by shorting the timer pin to ground. when in cc/cv charge mode, a battery charge cycle ter - minates when the current output from the charger falls to below one-tenth the maximum charge current , or i csmax , as programmed with r cs . the c/10 threshold current corresponds to 5mv across r cs . during lead-acid charging, the LTC4020 initiates float charging when the absorption stage charge current is re - duced to one-tenth of the programmed maximum current. when charging in cc mode, the current source function remains active indefinitely. there is no provision for bad battery detection if c /10 termination is used. timer: timed functions the LTC4020 supports timer based functions, where bat - tery charge cycle control occurs after a specific amount of time elapses . timer termination is engaged when a capacitor (c timer ) is connected from the timer pin to ground. c timer for a desired end-of-cycle time (t eoc ) follows the relation: c timer = t eoc ? 6.87 x 10 C2 (f) where t eoc is hours. a typical timer t eoc for li-ion charge cycle termination is three hours, which requires a 0.2f timer capacitor. the timer cycle starts when the charger transitions from constant-current to constant-voltage charging , thus, ter - mination at the end of the timer cycle only occurs if the charging cycle was successful . when timer termination is used, the stat1 status pin is pulled low during a charging cycle until the battery charge current falls below the c /10 threshold . the stat 1 pin stays high impedance with charge currents below c/10, but the charger continues to top off the battery until timer t eoc , when the LTC4020 terminates the charging cycle and the powerpath fet disconnects the battery from the dc/dc converter output. during lead-acid charging , the timer acts as an absorp - tion mode safety timer . normally, the ltc 4020 initiates float charging when the absorption stage charge current is reduced to one-tenth of the programmed maximum current, however, the maximum duration of absorption charging is limited by the timer. if the charge current does not fall to one-tenth of the programmed maximum current by t eoc , the LTC4020 forces the battery charger to begin float mode charging. a typical timer t eoc for lead-acid charging is six to eight hours, which is accommodated by a 0.47f timer capacitor. when charging in cc mode, after charge termination, once the timer reaches t eoc and the charge cycle terminates, input power or shdn must be cycled to initiate another battery charge cycle. a bad battery detection function is available during cc/ cv or lead-acid charging . this fault condition is achieved if the battery does not respond to preconditioning (v fb < 1.75v ), such that the charger remains in ( or enters) pre- condition mode after one-eighth of the programmed t eoc time. a bad battery fault halts the charging cycle , and the fault condition is reported on the status pins. the bad battery fault remains active until the battery voltage rises above the precondition threshold, or until power or shdn is cycled. battery temperature qualified charging: ntc the LTC4020 can accommodate battery temperature moni - toring by using an ntc (negative temperature co-efficient) thermistor close to the batter y pack . the temperature monitoring function is enabled by connecting a 10k, = 3380 ntc thermistor from the ntc pin to ground. if the ntc function is not desired , leave the pin unconnected. the ntc pin sources 50a, and monitors the voltage dropped across the 10k thermistor. when the voltage on this pin is above 1.35v (0c) or below 0.3v (40c), the battery temperature is out of range , and the LTC4020 triggers an ntc fault. the ntc fault condition remains until the voltage on the ntc pin corresponds to a temperature within the 0c to 40c range. both hot and cold thresholds incorporate hysteresis that corresponds to 5c. if higher operational charging temperatures are desired, the temperature range can be expanded by adding series resistance to the 10k ntc resistor. adding a 910 resistor will increase the effective hot temperature threshold to 45c. the effect of this additional resistance on the cold threshold is negligible. a pplica t ions i n f or m a t ion ltc 4020 4020fd 31 for more information www.linear.com/LTC4020 during an ntc fault, charging is halted and an ntc fault is indicated on the status pins. if timer termination is en - abled, the timer count is suspended and held until the fault condition is relieved . the rng/ss pin is also pulled low during this fault, to accommodate a graceful restart, in the event that a soft-start function is being incorporated (see dynamic charge current adjust and soft-start section). dc/dc converter: external compensation and filtering components the LTC4020 average current mode architecture employs two integrating compensation nodes. the current setting loop is compensated at the output of the current sense amplifier on the vc pin, generally with a series r-c net - work ( r vc , c vc ). the voltage generated on the vc pin is compared with an internal ramp, providing control of the converter duty cycle. the voltage loop is compensated at the output of the error amplifier on the ith pin, generally with a series r-c net - work (r ith , c ith ). the voltage on the ith pin is imposed onto the current sense amplifier, setting the current level to which the current loop will servo. while determining compensation components, the LTC4020 should initially be configured to eliminate any functional contribution from the battery charger section . this can be easily accomplished by connecting the ntc pin to ground, which disables all battery charging functions and puts the powerpath fet into a high impedance state. the current loop compensation ( vc pin) transfer function crossover frequency is typically set to approximately one- half of the switching frequency; the voltage loop compen- sation ( ith pin ) transfer function crossover frequency is typically set to approximately one-tenth of the switching frequency. compensation values must be tested at high and low input voltage operational limits, and also v in ~ v out , so that stable operation during all switching modes (buck, boost, buck-boost) is verified. if a network analyzer is not available for determining compensation values, use procedures as outlined in application note 19 for adjusting compensation. appli - cation note 19 can be found at http://www.linear.com/ docs/4176 . vc pin compensation: 1. v ntc = v fbmax = 0v 2. fix v in at typical voltage. 3. fix v out at v fb regulation voltage. a charged battery, battery simulator , or a 2-quadrant power supply can be used for v out . 4. impose 1v to 1.5v square wave (1khz) on ith pin 5. monitor inductor current using current probe 6. adjust compensation values as per an19 until response is critically damped ith pin compensation: 1. v ntc = 0v (disables charger) 2. bring to regulation (v fbmax = 2.75v) 3. step load current on output (25% to 75% of i max ) 4. monitor v out voltage 5. adjust compensation values as per an19 until response is critically damped and settled in ~10 to 25 cycles 6. v ntc = 0.8 (enable charger) 7. exercise battery charger and verify stability in all modes battery charger functions: filtering components voltage regulation loop (vfb): the charger voltage regulation loop monitors battery voltage, and as such is controlled by a very slow moving node. battery esr, however, can produce significant ac voltages due to ripple currents , which can cause unstable operation. this esr effect can be reduced by adding a capacitor to the vfb input, producing a low frequency pole. a pplica t ions i n f or m a t ion figure 18. vfb ripple suppression 4020 f18 v bat r fb1 r fb2 vfb LTC4020 c vfb ltc 4020 4020fd 32 for more information www.linear.com/LTC4020 figure 19. csn/csp ripple suppression current sense regulation loop (csn, csp): the charger current regulation loop monitors and regu - lates battery charge current . ripple voltage on the dc/dc converter output , however, gets directly imposed across the charger sense resistor, and can produce significant ripple currents. large ripple currents can corrupt low level current sensing, and can also cause unstable operation. this ripple current effect can be greatly reduced by adding a capacitor (c cs ) across the csn and csp pins, producing a low frequency pole with the two 100 resistors that are required for those pins. the filter frequency is typically set to reduce voltage ripple across the current sense inputs at the csp and csn pins to less than 1mv pp . the ripple-reduction filter on the current sense inputs cre - ates a phase shift in the charger current loop response, which can result in instability . a resistor (r csz ) in series with c cs creates a zero that can be employed to recover phase margin. this zero setting resistor will reintroduce ripple error, so r cs should be minimized. csout can be coupled into ith for a similar feedforward zero with r cs = 0. current sense information, or differential voltage at the csn to csp pins, is amplified by a factor of 20 then output on pin csout. this signal is compared to a reference voltage that is proportional to the maximum charge current at the input of a transconductance amplifier, which creates an error current that modulates the ith compensation pin. a feedforward zero can be employed to recover phase margin by putting a capacitor from the csout pin to the ith pin (c csout ). the output impedance of the csout pin is ~100k, so if compensation requirements are ap - propriate, the c csout capacitor can perform double-duty as both the primary pole ith capacitor along with a 100k zero-setting resistance, and as feed forward coupling from csout to ith. instant-on/ideal diode regulation loop (bgate): the instant-on function regulates the voltage across the powerpath fet by servoing the voltage at the bgate pin . gate capacitance of the powerpath fet is typically suf - ficient to stabilize this loop. additional capacitance can be added to the bga te pin (c bgate ) to stabilize the current foldback loop during instant-on operation if necessary: a pplica t ions i n f or m a t ion figure 20. instant-on/ideal diode compensation 4020 f20 100 v bat bat bgate csn LTC4020 c bgate r cs 4020 f19 100 v bat csn csp LTC4020 100 c cs r csz r cs layout considerations the LTC4020 is typically used in designs that involve substantial switching transients. the switch drivers on the ic are designed to drive large capacitances and, as such, generate significant transient currents themselves. supply bypass capacitor locations must be carefully considered to avoid corrupting the signal ground reference (sgnd) used by the ic. typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from sgnd, to which sensitive circuits such as the error amp reference and the current sense circuits are referred. effective grounding can be achieved by considering switch current in the ground plane, and the return current paths of each respective bypass capacitor. the v in bypass return, intv cc bypass return, and the sources of the ground- referred switch fets carry pgnd currents . sgnd originates at the negative terminal of the v out bypass capacitor , and is the small signal reference for the LTC4020. do not be tempted to run small traces to separate ground paths. a good ground plane is important as always, but pgnd referred bypass elements must be oriented such that transient currents in these return paths do not corrupt the sgnd reference. ltc 4020 4020fd 33 for more information www.linear.com/LTC4020 during the dead time between synchronous switch and main switch conduction , the body diode of the synchronous fet conducts inductor current. commutating the body diode requires a significant charge contribution from the main switch during initiation of main switch, creating a current spike in the main switch. at the instant the body diode commutates, a current discontinuity is created between the inductor and main switch, with parasitic inductance causing the switch node to transition in response to this discontinuity . high currents and exces - sive parasitic inductance can generate extremely fast v/ t times during this transition . these fast v/t transi - tions can sometimes cause avalanche breakdown in the synchronous fet body diode , generating shoot-through currents via parasitic turn-on of the synchronous fet. layout practices and component orientations that minimize parasitic inductance on the switched nodes is critical for reducing these effects. orient power path components such that current paths in the ground plane do not cross through signal ground areas. power ground currents are controlled on the LTC4020 via the pgnd pin, and this ground references the high current synchronous switch drive components, as well as the local intv cc supply. it is important to keep pgnd and sgnd voltages consistent with each other. separat- ing these grounds with thin traces is not recommended. when a ground referenced switch fet is turned off , gate drive currents return to the LTC4020 pgnd pin from the switch fet source . the boost supply refresh surge cur - rents also return through this same path. the switch fets must be oriented such that these pgnd return currents do not corrupt the sgnd reference . a pplica t ions i n f or m a t ion the high i/ t loop formed by the switch mosfets and the input capacitor (cv in ) should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. surface mount components are preferred to reduce parasitic inductances from component leads. switch path currents can be controlled by orient - ing switch fets , the switched inductor, and input and output decoupling capacitors in close proximity to each other . locate the intv cc , bst1, and bst2 decoupling capacitors in close proximity to the ic. these capacitors carry the switch fet gate drive currents . locate the small signal components away from high frequency switching nodes (tg1, bg1, tg2, bg2, sw1, sw2, bst1, bst2, and intv cc ). high current switching nodes are oriented across the top of the LTC4020 package to simplify layout and prevent corruption of the sgnd reference. locate the output and battery charger feedback resistors in close proximity to the LTC4020 and minimize the length of the high impedance feedback nodes. the sensvin and senstop traces should be routed together and sensbot and sensgnd should be routed together. keep these traces as short as possible, and avoid corruption of these lines by high current switching nodes. the LTC4020 packaging has been designed to efficiently remove heat from the ic via the exposed pad on the backside of the package. the exposed pad is soldered to a copper footprint on the pcb. the exposed pad is electri - cally connected to sgnd, so a good connection to a pcb ground plane effectively reduces the thermal resistance of the ic case to ambient air . please refer to ltc application note 136, which discusses guidelines, techniques, and considerations for switching power supply pcb design and layout: http://www.linear. com/docs/42146. ltc 4020 4020fd 34 for more information www.linear.com/LTC4020 a pplica t ions i n f or m a t ion LTC4020 constant-current/constant-voltage (cc/cv) charging diagram power available? indicate not charging bgate pulled low v fb > 2.5 ? ? v fb > 1.75? yes no no no no no no no no no no no no no yes 4020 cd01 yes yes yes yes yes yes v fb < 1.75? v fb = 2.4375v ntc out-of-range? charge at constant-current indicate charging trickle charge (7%) timer active? bgate pulled high indicate bad battery fault indicate ntc fault enable ideal diode function timers active? pause timers charge to fixed voltage timer active? run safety timer safety timer at eoc? stop charging indicate not charging stop charging i bat < c/10? i bat < c/10? start clear low battery and safety timers run low battery timer bgate pulled low indicate not charging indicate charging terminated v fb < 2.5 ? ? indicate not charging enable ideal diode function yes yes yes yes yes stop charging no timer at 1/8 eoc? yes v fb = 2.4375? no yes ltc 4020 4020fd 35 for more information www.linear.com/LTC4020 a pplica t ions i n f or m a t ion LTC4020 lead-acid charging diagram power available? indicate not charging bgate pulled low set absorption reference (2.5v) v fb < 2.5 ? ? v fb < 1.75? v fb > 1.75? yes no no no no no no no no no no no no no yes 4020 cd02 no yes yes yes yes yes yes v fb < 2.125? v fb = 2.4375v ntc out-of-range? charge at constant-current bgate pulled low set absorption reference (2.5v) timer active? stop charging bgate pulled high indicate not charging indicate not charging enable ideal diode function timers active? pause timers charge to fixed voltage timer active? run safety timer safety timer at eoc? set float reference (2.3125v) indicate float charging stop charging i bat < c/10? i bat < c/10? start clear low battery and safety timers trickle charge (7%) indicate bulk charging indicate absorption charging indicate bulk charging float reference set (2.3125)? yes yes yes no yes yes yes yes run low battery timer timer at 1/8 eoc? ltc 4020 4020fd 36 for more information www.linear.com/LTC4020 a pplica t ions i n f or m a t ion LTC4020 constant-current charging diagram power available? indicate not charging bgate pulled low clear timer no no no 4020 cd02 safety timer at eoc? ntc out-of-range? charge at constant-current bgate pulled low timer active? indicate ntc fault enable ideal diode function timers active? pause timer stop charging start indicate charging run timer yes yes yes no no yes yes indicate not charging enable ideal diode function stop charging ltc 4020 4020fd 37 for more information www.linear.com/LTC4020 typical a pplica t ions 5v to 30v to 6-cell lead-acid powerpath charger/system supply. 6a inductor current limit with 2.5a battery charge current limit. instant-on functionality incorporated for battery voltages below 12.25v, 14.4v absorption voltage, 13.3v float voltage,and 15.6v maximum output voltage (instant-on and ntc fault only). status pins light leds for visible charge-state monitoring. r sensea 0.008 si7272dp si7272dp si7272dp cmsh3-40ma si7272dp r senseb 0.008 56f 2 v in 5v to 30v LTC4020 sgnd back pgnd 4.7f sbr0560s1 r t , 130k pv in bg1 sw1 tg1 bst1 sgnd sensgnd 95.3k 2nf 2nf sensbot senstop sensvin rt shdn v in_reg mode stat1 stat2 timer rng_ss 6-cell lead-acid (12v) 4020 ta02 intvcc bg2 sw2 tg2 bst2 sgnd vc ith v fbmax i limit csout csp csn bgate bat v fbmin fbg vfb ntc 1f 284k 100k 1f 0.033f 33k 2.7k 15h xal1010-153meb sbr0560s1 bzx84c6v2l 680pf 100 si7135dp r cs 0.02 100 1f 20k 95.3k r ntc 10k 20k 0.33f 4.7f 0.1f 56f 3 v out 2.7k + + ltc 4020 4020fd 38 for more information www.linear.com/LTC4020 typical a pplica t ions 15v to 55v to 6-cell li-ion powerpath charger/system supply. 6a inductor current limit with 2.5a battery charge current limit. instant-on functionality for battery voltages below 20.4v, 24v charge termination voltage, and 26.4v maximum output voltage. status pins light leds for visible charge-state monitoring. r sensea 0.008 si7960dp si7960dp si7960dp mbrs360 si7960dp r senseb 0.008 4.7f 2 v in 15v to 55v LTC4020 sgnd back pgnd 10f sbr0560s1 r t , 100k pv in bg1 sw1 tg1 bst1 sgnd 100pf sensgnd sensbot senstop sensvin rt shdn shdn v in_reg mode stat1 stat2 timer rng_ss 4020 ta03 intv cc bg2 sw2 tg2 bst2 sgnd vc ith v fbmax i limit csout csp csn bgate bat v fbmin fbg vfb ntc 56f 2 0.1f 10nf 1f 56k xal1010-153meb 15h sbr0560s1 bzx84c6v2l 680pf 68pf 47k 100 r cs 0.02 si7461dp 215k 4.7f 4 56f 2 v out 24v at 3.5a max 0.033f 2.7k 2.7k 0.2f 105k 1f 100 24.9k 6-cell li-ion (24v) r ntc 10k + 24.9k 2.2f 4.7 215k 1nf 10k + ltc 4020 4020fd 39 for more information www.linear.com/LTC4020 typical a pplica t ions 9v to 55v to 9-cell lead-acid (18v) charger/system supply with no powerpath. external 5v regulator for boosted supplies. 5a inductor current limit with 1.67a battery charge current limit. 21.5v absorption voltage output, 19.9v float voltage output. r sensea 0.01 r senseb 0.01 si7960dp si7272dp cmsh3-40ma si7272dp si7850dp 56f 2 v in 9v to 55v LTC4020 sgnd back pgnd 4.7f sbr0560s1 r t , 100k 0.033f pv in bg1 sw1 tg1 bst1 sgnd sensgnd sensbot senstop sensvin rt shdn v in_reg mode stat1 stat2 timer rng_ss 9-cell lead-acid (18v) 4020 ta04 intv cc bg2 sw2 tg2 bst2 sgnd vc ith v fbmax i limit csout csp csn bgate bat v fbmin fbg vfb 10k ntc 1f 1.5nf 1f 249k 100k 43k 43k 15h sbr0560s1 bzx84c6v2l 680pf 100 1f 0.1f 4.7f v out 56f 3 lt3010-5 v in out shdn sense gnd + xal1010-153meb 100 r cs 0.03 100pf 0.33f 75.9k + ltc 4020 4020fd 40 for more information www.linear.com/LTC4020 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) p ackage descrip t ion please refer to http://www .linear.com/product/LTC4020#packaging for the most recent package drawings. ltc 4020 4020fd 41 for more information www.linear.com/LTC4020 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . r evision h is t ory rev date description page number a 01/14 changed v in to pv in modified i senstop operating current spec modified error amp transconductance spec changed c/10 detection enable units modified c/10 detection hysteresis spec changed conditions for gate clamp voltage changed conditions for bgate tests changed conditions for pin current (disabled) spec changed cathode to anode for bst1 changed anode to cathode for bst1 modified equations for t eoc and t pre and associated timer text modified equations for r fb1 /r fb2 and r min1 /r min2 changed cathode to anode for bst2 changed anode to cathode for bst2 modified error amplified transconductance modified step-up and step-down equations in switch fet section modified c timer equation and associated text modified typical applications circuit modified typical application circuit to 12-cell 2 to 5 3 3 4 4 4 5 5 8 8 9 10 12 12 14 24 30 38 42 b 09/14 added (application circuit on page 37) to efficiency curve title added ? unit to r fbg specification changed intv cc short circuit current limit vs temperature curve y-axis units to ma added text to the end of the ntc (pin 16) section corrected formula: (v outmax /2.75) - 1 changed bst1 on lower-right of block diagram to bst2; insert (v sens ) below 2mv near vc pin added 2v zener diode symbol from ntc pin (cathode) to ground (anode) added average to first line; change charge to average inductor in figure 6 title changed inductor to charge added ground symbol to bottom of ic symbol (backside connection) flipped pmos symbol vertically (si7461dp); add ground symbol to bottom of ic symbol (backside connection) added ground symbol to bottom of ic symbol (backside connection) moved connection of bzx84c6v2l anode from bg2 to sw2 (diode between bst2 and sw2); add ground symbol to bottom of ic symbol (backside connection) 1 5 6 10 12 14 15 23 28 37 38 39 42 c 09/15 added pin names to typical application ic drawing added text to end of sensbot (5) pin description section changed text in rng/ss section: inductor to charge changed i limit text, ...pin, so maximum charge current..." to ...pin, so maximum inductor current..." changed operation section to a 0.47f capacitor on the timer pin is typically used, which generates a 6.8 hour absorption stage safety timeout changed c sensbot,sensgnd to c sensb changed ...bgate pin to ground to ...bgate pit to csn changed csn to csn. replaced r cs with r csz in the text and in figure 19. replaced r sense with r cs in figure 19 replaced r sense with r cs in schematic 1 8 9 12 20 22 28 32 37-39, 42 d 04/16 modified bulk capacitance equation 24 ltc 4020 4020fd 42 for more information www.linear.com/LTC4020 ? linear technology corporation 2013 lt 0416 rev d ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC4020 r ela t e d p ar t s typical a pplica t ion remote 24v to 55v (48v system) input to 12-cell li-ion (48v) powerpath charger/system supply. 5a inductor current limit with 2.5a battery charge current limit. minimum v in is 24v as input regulation limits voltage loss due to line impedance. battery termination voltage is 48v with maximum output voltage of 52.8v. instant-on functionality limits minimum regulated output voltage to 40.8v. part number description comments ltc3789 high efficiency, synchronous, 4 switch buck-boost controller improved ltc3780 with more features lt3845 high voltage synchronous current mode step-down controller for medium/high power, high efficiency supplies lt3650 high voltage 2a monolithic li-ion battery charger 3mm 3mm dfn-12 and msop-12 packages lt3651 high voltage 4a monolithic li-ion battery charger 4a synchronous version of lt3650 family lt3652/lt3652hv power tracking 2a battery chargers multi-chemistry, onboard termination ltc4009 high efficiency, multi-chemistry battery charger low cost version of ltc4008, 4mm 4mm qfn-20 ltc4012 high efficiency, multi-chemistry battery charger with powerpath control similar to ltc4009 adding powerpath control lt3741 high power, constant current, constant voltage, step-down controller thermally enhanced 4mm 4mm qfn and 20-pin tssop lt8705 80v in /v out sync buck-boost 4-sw controller single inductor, tssop-38 and 5mm 7mm qfn-38 r sensea 0.01 si7850dp si7850dp si7850dp si7850dp r senseb 0.01 v in 24v to 55v LTC4020 sgnd back pgnd r t , 100k pv in bg1 sw1 tg1 bst1 sgnd sensgnd sensbot senstop sensvin rt shdn v in_reg mode timer rng_ss 12-cell li-ion (48v) 4020 ta05 intv cc bg2 sw2 tg2 bst2 sgnd vc ith v fbmax i limit csout csp csn bgate bat v fbmin fbg vfb ntc 56f 2 1f 191k 10k 12k stat1 stat2 1f sbr0560s1 4.7f 33k 100 r cs 0.02 si7465dp sbr0560s1 bzx84c6v2l 680pf 100 365k 1.5nf 2nf 0.33f 356k 20k 20k 1f r ntc 10k 0.1f 4.7f 56f 2 v out ihlp-5050fd-5a mbrs360 22h 0.033f + + ltc 4020 4020fd |
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